Asus P7H55D-M EVO Bedienungsanleitung Seite 77

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ASUS P7H55D-M EVO 3-21
Chapter 3
CPU Ratio Setting [Auto]
Allows you to set the ratio between the CPU Core Clock and the BCLK Frequency. Use <+>
and <-> keys to adjust the ratio. The valid value ranges vary according to your CPU model.
C1E Support [Enabled]
[Enabled] Enables the C1E support function. This item should be enabled in order to
enable the Enhanced Halt Sate.
[Disabled] Disables this function.
Hardware Prefetcher [Enabled]
[Enabled] The processor fetches data and instructions from the memory into the
cache that are likely to be required in the near future. This reduces the
latency associated with memory reads.
[Disabled] Disables this function.
Adjacent Cache Line Prefetch [Enabled]
[Enabled] The processor fetches the currently requested cache line, as well as the
subsequent cache line. This reduces the cache latency by making the next
cache line immediately available if the processor requires it as well.
[Disabled] The processor fetches only the currently requested cache line.
Max CPUID Value Limit [Disabled]
[Enabled] Allows legacy operating systems to boot even without support for CPUs
with extended CPUID functions.
[Disabled] Disables this function.
Intel(R) Virtualization Tech [Enabled]
[Enabled] Allows a hardware platform to run multiple operating systems separately
and simultaneously, enabling one system to virtually function as several
systems.
[Disabled] Disables this function.
CPU TM function [Enabled]
[Enabled] Enables the overheated CPU to throttle its clock speed to cool down.
[Disabled] Disables this function.
Execute Disable Bit Capability [Enabled]
[Enabled] Enables the No-Execution Page Protection Technology.
[Disabled] Forces the XD feature ag to always return to zero (0).
Intel(R) HT Technology [Enabled]
The Intel Hyper-Threading Technology allows a hyper-threading processor to appear as two
logical processors to the operating system, allowing the operating system to schedule two
threads or processes simultaneously.
[Enabled] Two threads per activated core are enabled.
[Disabled] Only one thread per activated core is enabled.
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